In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar FET structure shown in FIG. 1, a FinFET 100 generally includes two or more parallel silicon fin structures (or simply “fins”) 104 and 106. These structures are typically formed using a silicon-on-insulator (SOI) substrate (not shown) or alternatively on a bulk substrate, with fins 104 and 106 extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 102 “wraps around” three sides of both fins 104 and 106, and is separated from the fins by a standard gate oxide layer 103. While FIG. 1 illustrates only one gate structure 102 wrapped around fins 104 and 106, two, three or more parallel gate structures can be wrapped around the fins. Fins 104 and 106 may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 103. The width of the gate, indicated by double-headed arrow 108, determines the effective channel length of the device.
In order to control the threshold voltage (Vth) of a FinFET device, various techniques are currently being applied in the art. One technique involves varying the thickness of the fin. Another technique involves varying the thickness of the gate. Yet another technique involves doping the fin channel. Each of these techniques, however, has ultimately proven unsatisfactory due to the limited effect they have on Vth, and the inherent performance trade-offs that come with increasing the thickness of the fin or the gate.
Accordingly, it is desirable to provide FinFET structures and methods for fabricating FinFET structures with improved control over the Vth. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.